An open-source toolchain to go from SystemVerilog to Silicon

This is summarized by this chart, credit to Mithro for this:

Figure 1: A flowchart detailing the different open-source tools used to synthesize SystemVerilog into synthesizable netlists and fabricatable circuit definitions.

When using the SkyWater 130nm PDK, be sure to use the efabless fork available from OpenPDK. The Google version is unpleasant to use in my experience.